feat(v-prime): holo-mesh-2x2 4-die scale-out (4×) · L-DPC25 Lane V'

1. Background

Lane A' (holo_noc_1cycle, merged at 78362042 on #13) established a 1-cycle inter-die NoC stub for 2-die TTSKY26c HOLOGRAPHIC packaging. Lane W (#14) added the BitROM storage layer that this NoC fabric connects. Lane V' extends the silicon fabric from a 2-die point-to-point link to a 2×2 mesh enabling 4-die scale-out — the HOLOGRAPHIC TTSKY26c packaging target.

This lane is a LANG→SI extension: OP_BITROM_READ 0xE0 storage data now routes across 4 dies via XY-routed mesh hops. No new Sacred ROM opcode is introduced (range 0xD0..0xE0 is R18-frozen). The mesh fabric connects 4 dies each running the 3-opcode QB ISA.

Algebraic anchor: φ² + φ⁻² = 3 · DOI 10.5281/zenodo.19227877

2. Hypothesis (G1)

H_V': The 2×2 holo-mesh delivers 4× throughput vs single-die Lane A', with 1-cycle per hop latency and zero deadlock.

Falsified iff (a) any RTL * operator, OR (b) any single-hop path takes > 1 cycle, OR (c) any deadlock under uniform-random traffic, OR (d) mesh end-to-end latency > Lane A' latency + 1 cycle.

3. Method

Lane decomposition:

Hard rules enforced:

• R-SI-1: zero * operators in all RTL files (grep-verified)
• R18 LAYER-FROZEN: rtl/holo_noc_1cycle.sv unmodified; additive only
• R1 CROWN-rule: no Python/bash in committed code (Rust/SV only)

4. Pre-Registration (G2)

5. Falsification Witnesses (R7)

Three #[test] functions in falsif/tests/v_prime_witness.rs:

SV testbench falsification in tb/tb_holo_mesh_2x2.sv:

• TC1: corner-to-corner 2-hop latency ≤ 2 cycles
• TC2: 4-node simultaneous inject — no deadlock
• TC3: 1000 LFSR-driven random patterns — no timeout, no latency > 2

6. Deliverables

• rtl/holo_mesh_router.sv — 147 LOC, zero *, 1-cycle XY router
• rtl/holo_mesh_2x2.sv — 230 LOC, zero *, R18-clean additive top
• tb/tb_holo_mesh_2x2.sv — 366 LOC, TC1+TC2+TC3, 1000 random patterns
• falsif/tests/v_prime_witness.rs — 360 LOC, 3 #[test] witnesses
• docs/lever-stack/lane-v-prime.md — full spec with hop matrix + throughput model

7. Quality Gates

• R-SI-1 CI (grep for * in RTL) — expected GREEN (verified locally)
• GitGuardian secret scan — no secrets in committed code
• Rust cargo test -p holo-falsif — 3 new tests in v_prime_witness.rs
• SV testbench simulation — TC1+TC2+TC3 PASS

8. Forbidden Actions

• ❌ Any * operator in RTL
• ❌ Mutating Lane A' rtl/holo_noc_1cycle.sv from feat(a-prime): holo-noc-1cycle inter-die NoC (P4 falsification) · L-DPC24 Lane A' #13
• ❌ Python or bash in committed code
• ❌ Admin-merging this PR (parent decides)
• ❌ Claiming PASS without conclusion=SUCCESS from CI

9. References

10. Battle Cry

φ² + φ⁻² = 3 · 4× mesh scale-out · 2×2 holo · NEVER STOP · LANG→SI · DOI 10.5281/zenodo.19227877

Refs #104